HMC704LP4E【PDF 28/44 页】IC FRACT-N PLL 16BIT 24QFN

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HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

open Mode - Serial Port rEaD operation

A typical READ cycle is shown in Figure 39.

In general, in Open Mode the LD_sDO line is always active during the WRITE cycle. During any Open Mode sPI cycle

LD_sDO will contain the data from the current address written in “Reg 00h”[4:0]. If “Reg 00h”[4:0] is not changed then

the same data will always be present on LD_sDO when an Open Mode cycle is in progress. If it is desired to READ from

a specific address, it is necessary in the first sPI cycle to write the desired address to “Reg 00h”[4:0], then in the next

sPI cycle the desired data will be available on LD_sDO.

An example of the Open Mode two cycle procedure to read from any random address is as follows:

a. The Master (host), on the first 24 falling edges of sCLK places 24 bit data, d23:d0, MsB first, on sDI

as shown in Figure 39. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on

the next cycle.

b. the slave (PLL) shifts in data on sDI on the first 24 rising edges of sCLK

c. Master places 5 bit register address , r4:r0, ( the address the READ ADDREss register), MsB first,

on the next 5 falling edges of sCLK (23-29). r4:r0=00000.

d. slave shifts the register bits on the next 5 rising edges of sCLK (23-29).

e. Master places 3 bit chip address, a2:a0, MsB first, on the next 3 falling edges of sCLK (30-32).Chip

address is always 000 for RF PLL-VCOs.

slave shifts the chip address bits on the next 3 rising edges of sCLK (30-32).

g. Master asserts sEN after the 32nd rising edge of sCLK.

h. slave registers the sDI data on the rising edge of sEN.

Master clears sEN to complete the address transfer of the two part READ cycle.

If we do not wish to write data to the chip at the same time as we do the second cycle , then it is

recommended to simply rewrite the same contents on sDI to Register zero on the READ back part

of the cycle.

k. Master places the same sDI data as the previous cycle on the next 32 falling edges of sCLK.

slave (PLL) shifts the sDI data on the next 32 rising edges of sCLK.

m. slave places the desired data (i.e. data from address in “Reg 00h”[4:0 ]) on LD_sDO on the next 32

rising edges of sCLK. Lock Detect is disabled.

n. Master asserts sEN after the 32nd rising edge of sCLK to complete the cycle and revert back to

Lock Detect on LD_sDO.

Note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the LD_sDO output to prevent a pos-

sible contention issue.

table 12. SPi open Mode - read timing characteristics

Parameter

Conditions

Min.

Typ.

Max.

Units

sDI setup time

sDI hold time

sEN low duration

sEN high duration

sCLK Rising Edge to sDO time

8.2+0.2ns/pF

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